Power management for a peripheral component interconnect environment with auxiliary power

ABSTRACT

A circuit and method thereof for arbitrating between a plurality of power sources connected to a computer system peripheral device. The circuit includes a first circuit subassembly coupled to a first power source and a second power source. The first circuit subassembly conducts current from the first power source when power is not available from the second power source, and otherwise conducts current from the second power source. The circuit also includes a second circuit subassembly coupled between the first circuit subassembly and a third power source. The second circuit subassembly conducts current from the third power source when the third power source is available and otherwise conducts current from the first circuit subassembly. The second circuit subassembly comprises a first component, a second component and a third component. The first component is coupled to the third power source and the first circuit subassembly. The first component conducts current from the first circuit subassembly when power is not available from the third power source and otherwise substantially does not conduct current. The second component is coupled to the third power source and the first component. The second component conducts current from the first component when power is available from the third power source and otherwise substantially does not conduct current. The third component is coupled to the first component, the second component and the third power source. The third component conducts current from the third power source when power is available from the third power source.

TECHNICAL FIELD

The present invention generally pertains to the field of computernetworking. More particularly, the present invention pertains to powermanagement in a network adapter with more than one power source, such asa network adapter equipped with remote wakeup capability.

BACKGROUND ART

A computer system's functionality is dramatically enhanced by couplingstand-alone computers together to form a computer network. In a computernetwork, users may readily exchange files, share information stored on acommon database, pool resources, and communicate via e-mail and videoteleconferencing. Another advantage of computer networks is that theycan be accessed from remote locations via a modem or various other typesof communication equipment.

One popular type of computer network is known as a local area network(LAN). LANs connect multiple computers together such that the users ofthe computers can access the same information and share data. Typically,in order to be connected to a LAN, a general purpose computer requires aperipheral device generally known as a network adapter or networkinterface card (NIC). Essentially, the NIC works with the operatingsystem and central processing unit (CPU) of the host computer to controlthe flow of information over the LAN. NICs may also be used to connect acomputer to the Internet.

Remote access to a computer network (e.g., a LAN) is facilitated byproviding the capability to start or wake up a computer from a remotelocation. This feature is advantageous to a user desiring access to acomputer from a remote location. This feature is also advantageous to anetwork administrator, allowing the administrator to perform, forexample, maintenance activities on a computer system from a remotelocation.

A standard has been developed for allowing a networked computer which isin sleep mode to be awakened. More specifically, Advanced Micro Devices(AMD) of Santa Clara, Calif., has developed a technology referred to asthe Magic Packet technology. In the Magic Packet technology, assuming,for example, that an Ethernet controller is running and communicatingwith the network, the computer's power management hardware or softwareputs the Ethernet controller into the Magic Packet mode prior to thesystem going to sleep. Once in the sleep mode, the computer will beawakened when a Magic Packet is detected. That is, incoming data will bemonitored until the specific sequence comprising the Magic Packet isdetected. The Magic Packet technology and the associated standard(generally referred to as the Wakeon LAN standard) are well known in theart.

Accordingly, some NICs are designed to detect a Magic Packet and toawaken the computer (or selected components within the computer) inresponse. These NICs are typically connected in a standard fashion tothe computer (e.g., to the computer's motherboard) via a bus such as aPCI (peripheral component interconnect) bus. These NICs also areconnected to the motherboard via a separate cable (e.g., a remote wakeupcable). Thus, NICs that provide a remote wakeup capability typicallyhave a primary power source from the motherboard and an auxiliary powersource from the remote wakeup cable. When the computer is powered on andawake, power to the NIC is provided over the PCI bus from the primarypower source, typically five volts (5V). When the computer system is inthe sleep mode, power to the NIC is provided over the remote wakeupcable from the auxiliary power source, typically also 5V. Therefore,when a Magic Packet is received, the NIC will have power and hence theability to wake up. The NIC also can then send a PME (power managementevent) signal via the remote wakeup cable to wake up the computer.

The prior art is problematic because the presence of more than one powersource can cause a power contention issue. If power is being provided byone source (for example, by the auxiliary power source), it is notnecessary for the other source (in this case, the primary power source)to provide power. In fact, using power concurrently from both sourcesmay cause damage to some of the components in the NIC. Also, switchingto different power sources during the power down mode can cause faultsin the NIC.

This problem is aggravated if an additional power source is introduced.For example, revision 2.2 of the PCI specification (“PCI 2.2”) requiresthe addition of another auxiliary power source. In accordance with PCI2.2, pin A14 of the PCI bus provides a 3.3V auxiliary power source tothe NIC. Thus, a NIC with remote wakeup capability and adapted toaccommodate an additional auxiliary power source (such as that specifiedby PCI 2.2) can have three power sources, aggravating the powercontention issue described above.

Thus, a need exists for a device or method that addresses the powercontention problem so that components do not inadvertently receive powerfrom more than one source when multiple power sources are present in aperipheral device (such as a NIC). A need also exists for a device ormethod that addresses the above need and can be applied to a legacydevice (such as a NIC) to allow the legacy device to accommodateadditional power sources (such as that specified in PCI 2.2). A furtherneed exists for a device or method that addresses the above needs andallows the peripheral device to select one power source versus anotherdepending on the mode in which the computer and peripheral device arecurrently operating (e.g., sleep mode versus awake). The presentinvention provides a novel solution to these needs.

DISCLOSURE OF THE INVENTION

The present invention provides a device and method thereof that addressthe power contention problem so that components do not inadvertentlyreceive power from more than one source when multiple power sources arepresent in a peripheral device (such as a network interface card [NIC]).The present invention also provides a device and method thereof that canbe applied to a legacy device (such as a NIC) to allow the legacy deviceto accommodate additional power sources (such as that specified inrevision 2.2 of the PCI specification). The present invention alsoprovides a device and method thereof that allow the peripheral device toselect one power source versus another depending on the mode in whichthe computer and peripheral device are currently operating (e.g., sleepmode versus awake).

Specifically, in one embodiment of the present invention, the circuitand method thereof arbitrate between a plurality of power sourcesconnected to a computer system peripheral device. The circuit includes afirst circuit subassembly coupled to a first power source and a secondpower source. The first circuit subassembly conducts current from thefirst power source when power is not available from the second powersource, and otherwise conducts current from the second power source.

In the present embodiment, the circuit also includes a second circuitsubassembly coupled between the first circuit subassembly and a thirdpower source. The second circuit subassembly conducts current from thethird power source when the third power source is available andotherwise conducts current from the first circuit subassembly. Thesecond circuit subassembly comprises a first component, a secondcomponent and a third component.

In the present embodiment, the first component is coupled to the thirdpower source and the first circuit subassembly. The first componentconducts current from the first circuit subassembly when power is notavailable from the third power source and otherwise substantially doesnot conduct current. The second component is coupled to the third powersource and the first component. The second component conducts currentfrom the first component when power is available from the third powersource and otherwise substantially does not conduct current. The thirdcomponent is coupled to the first component, the second component andthe third power source. The third component conducts current from thethird power source when power is available from the third power source.

In one embodiment, a fourth component is coupled to the first component,the second component and the first circuit subassembly. The fourthcomponent conducts current from the first circuit subassembly when poweris available from the third power source and otherwise substantiallydoes not conduct current. Also, a fifth component is coupled to thesecond component and the fourth component. The fifth component conductscurrent from the fourth component when power is not available from thethird power source and otherwise substantially does not conduct current.In addition, a sixth component is coupled to the fourth component andthe first circuit subassembly. The sixth component conducts current fromthe first circuit subassembly when power is not available from the thirdpower source and otherwise substantially does not conduct current.

In one embodiment, the first circuit subassembly includes a seventhcomponent coupled between the first (e.g., primary) power source and thesecond (e.g., auxiliary) power source. The seventh component conductscurrent from the first power source when power is not available from thesecond power source. An eighth component integral with the seventhcomponent conducts current from the first power source in combinationwith the seventh component and substantially prevents current fromflowing from the second power source to the first power source. Thus, inthis embodiment, power from the second power source is used when poweris available from the second power source, and otherwise power from thefirst power source is used.

In one embodiment, the first component, second component, thirdcomponent, fourth component, fifth component and sixth component aretransistors, specifically, field effect transistors (FETs). In oneembodiment, the seventh component is a FET and the eighth component is adiode.

In one embodiment, the first power source is a five volt (5V) sourceconnected to the peripheral device via a peripheral componentinterconnect (PCI) bus, the second power source is an auxiliary 5Vsource connected to the peripheral device via a remote wakeup cable, andthe third power source is an auxiliary 3.3V source connected to theperipheral device substantially in accordance with PCI specificationrevision 2.2.

These and other advantages of the present invention will no doubt becomeobvious to those of ordinary skill in the art after having read thefollowing detailed description of the preferred embodiments which areillustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention:

FIG. 1 is a block diagram of an exemplary computer system in accordancewith one embodiment of the present invention.

FIG. 2 is a block diagram showing a network interface card with remotewakeup capability connected to the computer system of FIG. 1 inaccordance with one embodiment of the present invention.

FIG. 3 is a block diagram of the network interface of FIG. 2 inaccordance with one embodiment of the present invention.

FIG. 4 is a schematic diagram of a first circuit subassembly used by thenetwork interface card of FIG. 3 in accordance with one embodiment ofthe present invention.

FIG. 5 is a schematic diagram of a second circuit subassembly used bythe network interface card of FIG. 3 in accordance with one embodimentof the present invention.

FIG. 6 is a flowchart of a process used to arbitrate between multiplepower sources in accordance with one embodiment of the presentinvention.

The drawings referred to in this description should be understood as notbeing drawn to scale except if specifically noted.

BEST MODE FOR CARRYING OUT THE INVENTION

Reference will now be made in detail to the preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone of ordinary skill in the art that the present invention may bepracticed without these specific details. In other instances, well knownmethods, procedures, components, and circuits have not been described indetail as not to unnecessarily obscure aspects of the present invention.

Some portions of the detailed descriptions which follow are presented interms of procedures, logic blocks, processing, and other symbolicrepresentations of operations on data bits within a computer memory.These descriptions and representations are the means used by thoseskilled in the data processing arts to most effectively convey thesubstance of their work to others skilled in the art. In the presentapplication, a procedure, logic block, process, etc., is conceived to bea self-consistent sequence of steps or instructions leading to a desiredresult. The steps are those requiring physical manipulations of physicalquantities. Usually, though not necessarily, these quantities take theform of electrical or magnetic signals capable of being stored,transferred, combined, compared, and otherwise manipulated in a computersystem. It has proved convenient at times, principally for reasons ofcommon usage, to refer to these signals as bits, values, elements,symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the followingdiscussions, it is appreciated that throughout the present invention,discussions utilizing terms such as “selecting,” “conducting,” “using”or the like, refer to the actions and processes of a computer system, orsimilar electronic computing device. The computer system or similarelectronic computing device manipulates and transforms data representedas physical (electronic) quantities within the computer system'sregisters and memories into other data similarly represented as physicalquantities within the computer system memories or registers or othersuch information storage, transmission, or display devices. The presentinvention is also well suited to the use of other computer systems suchas, for example, optical and mechanical computers.

FIG. 1 illustrates an exemplary computer system 100 upon whichembodiments of the present invention may be practiced. The computersystem 100 is used in combination with a peripheral component to performthe present method in accordance with one embodiment of the presentinvention. It is appreciated that system 100 is exemplary only and thatthe present invention can operate within a number of different computersystems including general purpose networked computer systems, embeddedcomputer systems, and stand alone computer systems. Additionally,computer system 100 is well adapted to having computer readable mediasuch as, for example, a floppy disk, a compact disc, and the likecoupled thereto. Such computer readable media is not shown coupled tocomputer system 100 in FIG. 1 for purposes of clarity.

Computer system 100 includes an address/data bus 102 for communicatinginformation. In the present embodiment, bus 102 is a PCI (peripheralcomponent interconnect) bus substantially compliant with revisions 2.1and 2.2 of the PCI specification. Accordingly, the discussion herein isin the context of a PCI bus; however, it is appreciated that variousother types of buses can be used in accordance with the presentinvention. It is further appreciated that other revisions of the PCIspecification may be utilized with the present invention. Additionalinformation regarding bus 102 is provided below in conjunction with FIG.3.

Continuing with reference to FIG. 1, central processor unit 104 iscoupled to bus 102 for processing information and instructions. Computersystem 100 can also include data storage features such as a computerusable volatile memory 106 (e.g., random access memory [RAM]) coupled tobus 102 for storing information and instructions for central processorunit 104, computer usable non-volatile memory 108 (e.g. read only memory[ROM]) coupled to bus 102 for storing static information andinstructions for the central processor unit 104, and a data storagedevice 110 (e.g., a magnetic or optical disk and disk drive) coupled tobus 102 for storing information and instructions. Computer system 100can also include an optional alphanumeric input device 112 includingalphanumeric and function keys. Alphanumeric input device 112 is coupledto bus 102 for communicating information and command selections tocentral processor unit 104. Computer system 100 can also optionallyinclude a cursor control device 114 coupled to bus 102 for communicatinguser input information and command selections to central processor unit104. Computer system 100 also can include an optional display device 116coupled to bus 102 for displaying information.

Optional display device 116 may be a liquid crystal device, cathode raytube, or other display device suitable for creating graphic images andalphanumeric characters recognizable to a user. Optional cursor controldevice 114 allows the computer user to dynamically signal thetwo-dimensional movement of a visible symbol (cursor) on a displayscreen of display device 116. Many implementations of cursor controldevice 114 are known in the art including a trackball, mouse, touch pad,joystick or special keys on alphanumeric input device 112 capable ofsignaling movement of a given direction or manner of displacement.Alternatively, it will be appreciated that a cursor can be directedand/or activated via input from alphanumeric input device 112 usingspecial keys and key sequence commands. The present invention is alsowell-suited to directing a cursor by other means such as, for example,voice commands.

With reference still to FIG. 1, significantly, a network interface card(NIC) 118 coupled to bus 102 is connected to a network 120 and controlsthe flow of information to and from NIC 118 over network 120. Incomingdata packets arrive at NIC 118 via network 120 and are typically storedin memory of NIC 118 before being transferred to other hardware andsoftware of computer system 100. In accordance with the presentinvention, NIC 118 is equipped with a remote wakeup function. Variousknown remote wakeup techniques may be used in accordance with thepresent invention. One such remote wakeup technique is the known MagicPacket technique utilizing the Wakeon LAN (local area network) standard.A more detailed discussion of NIC 118 in furtherance of the presentinvention is found below.

Refer next to FIG. 2, which is a block diagram showing NIC 118 (withremote wakeup capability) connected to computer system 100 in accordancewith the present embodiment of the present invention. NIC 118 is coupledto computer system 100 via bus 102 as described above. In one embodimentin which NIC 118 has remote wakeup capability, NIC 118 is also coupledto computer system 100 via remote wakeup cable 205.

In the present embodiment, bus 102 provides five volts (+5V) of power toNIC 118; in the discussion herein, this power is referred to as “primarypower” or “+5V primary.” The primary power is used to power NIC 118when, for example, computer system 100 is powered on and not in thesleep mode, or when remote wakeup cable 205 is not attached.

When the remote wakeup function is present, +5V is also provided to NIC118 using remote wakeup cable 205; in the discussion herein, this isreferred to as “first auxiliary power” or “+5V auxiliary.” The firstauxiliary power is used to power NIC 118 when it is available. In otherwords, +5V auxiliary power supersedes the +5V primary power, andcontinues to be available when computer system 100 is in the sleep mode.In this manner, power remains available to NIC 118 so that it has thecapability to wake up upon receiving a particular signal (e.g., a MagicPacket).

Additional auxiliary power of +3.3V can also be provided to NIC 118 viabus 102. For example, revision 2.2 of the PCI specification requiresthat +3.3V of auxiliary power be provided via pin A14 of bus 102. In thediscussion herein, this is referred to as “second auxiliary power” or“+3.3V auxiliary.” The +3.3V auxiliary power is not used if the +5Vauxiliary power provided by the remote wakeup cable is available; thatis, +3.3V auxiliary power is only used when computer system 100 ispowered down without +5V auxiliary power.

Thus, NIC 118 has multiple power sources: for bus 102 substantiallycompliant with revision 2.1 of the PCI specification (“PCI 2.1”), NIC118 (with remote wakeup capability) has at least two (2) power sources,and for bus 102 substantially compliant with revision 2.2 of the PCIspecification, NIC 118 (with remote wakeup capability) has three (3)power sources. It is appreciated that additional power sources, or powersources of different voltages, may be utilized in accordance with thepresent invention. It is further appreciated that the present inventionmay be used when the remote wakeup cable is not present for PCI 2.1 orwhen the system is not compliant with revision 2.2 of the PCIspecification, as will be seen. Thus, the present invention can beutilized with legacy devices.

FIG. 3 is a block diagram providing further details of NIC 118 inaccordance with the present embodiment of the present invention. Asdescribed above, +5V primary power (330) and +3.3V auxiliary power (332)are provided to NIC 118 from computer system 100 via bus 102 for asystem compliant with revision 2.2 of the PCI specification.

Also as described above, power for the remote wakeup function isprovided to NIC 118 via remote wakeup cable 205. Remote wakeup cable 205is connected to NIC 118 using connector 300. In the present embodiment,connector 300 is a 3-pin plug comprised of a first pin 302, a second pin304 and a third pin 306. In this embodiment, first pin 302 provides +5Vauxiliary power to NIC 118. Second pin 304 is a ground, and third pin306 provides a power management event (PME) signal that is used to wakeup computer system 100. In the present embodiment, third pin 306 (PME)is connected to application specific integrated circuit (ASIC) 320,which is prompted to wake up computer system 100 when NIC 118 receives awakeup signal (such as a Magic Packet) (the connections from third pin306 to ASIC 320 and from ASIC 320 to computer system 100 are not shown).

In accordance with the present invention, NIC 118 also includes firstcircuit subassembly 310 and second circuit subassembly 312 that are usedfor arbitrating between multiple power sources connected to NIC 118,thereby addressing power contention issues. First circuit subassembly310 is used to arbitrate between the +5V primary power 330 and +5Vauxiliary power 302, and provides +5V to second circuit subassembly 312.Second circuit subassembly 312 is used to arbitrate between the +5V fromfirst circuit subassembly 310 and +3.3V auxiliary power 332 inaccordance with the present invention. First circuit subassembly 310 andsecond circuit subassembly 312 are described below in conjunction withFIG. 4 and FIG. 5, respectively.

In addition to ASIC 320, NIC 118 can also include electrically erasableprogrammable ROM (EEPROM) 322 and boot ROM 324. In one embodiment, ASIC320 includes a voltage regulator to convert voltage from +5V to 3.3V.This internal voltage regulator can regulate +5V to +3.3V, which canthen be used to power EEPROM 322 and boot ROM 324 when +3.3V auxiliarypower 332 is not available.

FIG. 4 is a schematic diagram illustrating first circuit subassembly 310in accordance with one embodiment of the present invention. Firstcircuit subassembly 310 receives either +5V primary power 330 from bus102 (FIG. 3) or +5V auxiliary power 302 from remote wakeup cable 205(FIG. 3). In accordance with the present invention, first circuitsubassembly 310 passes power from one source or the other but not bothto second circuit subassembly 312, thereby addressing the potentialpower contention issue that would otherwise occur. In the presentembodiment, first circuit subassembly 310 conducts the power from +5Vauxiliary power 302 when that source of power is available (e.g., whenNIC 118 has the remote wakeup function) even when +5V primary power 330is available. If +5V auxiliary power 302 is not available (e.g., NIC 118does not have the remote wakeup function), then +5V primary power 330 isused (when computer system 100 is powered on and not in the sleep mode).

Continuing with reference to FIG. 4, first circuit subassembly 310includes a component (410) that conducts power (e.g., current) from +5Vprimary power 330 when +5V auxiliary power 302 is not present. In thepresent embodiment, component 410 is a transistor, specifically an-channel field effect transistor (FET) (hereinafter, n-channel FET410). Intrinsic to n-channel FET 410 is a diode 420. The orientation ofn-channel FET 410 allows the intrinsic diode 420 to substantiallyprevent power (current) from flow from +5V auxiliary power 302 (whenpresent) to +5V primary power 330. In the present embodiment, n-channelFET 410 is designed such that when V_(GS) is greater than or equal to+5V, then n-channel FET 410 is on; otherwise, it is off. It isappreciated that n-channel FET 410 can be designed to be on/off forother values of V_(GS) in accordance with the present invention.

In accordance with the present embodiment of the present invention,first circuit subassembly 310 works as follows. In the case in whichboth +5V auxiliary power 302 and +5V primary power 330 are present, NIC118 will have remote wakeup capability and, accordingly, connector 300including second pin 304 (ground) is also present. Thus, the +12 Vsource (from bus 102) is grounded and V_(GS) is −5V (0 V at the gate [G]terminal and +5V at the source [S] terminal of n-channel FET 410).Consequently, n-channel FET 410 is off and power from +5V auxiliarypower 302 is provided to second circuit subassembly 312. Diode 420intrinsic to n-channel FET 410 protects +5V primary power 330 againstback drive current from +5V auxiliary power 302.

In the case in which computer system 100 (FIG. 3) is powered down (e.g.,the computer system is in the sleep mode), then only +5V auxiliary power302 is available. As can be seen from FIG. 4, this power is provided tosecond circuit subassembly 312 directly, and no power will be availablefrom +5V primary power 330. Diode 420 intrinsic to n-channel FET 410protects +5V primary power 330 against back drive current from +5Vauxiliary power 302.

In the case in which only +5V primary power 330 is present, NIC 118 doesnot have remote wakeup capability, and so connector 300 including secondpin 304 (ground) is not present. Thus, V_(GS) is +7V and consequentlyn-channel FET 410 is on. Power from +5V primary power 330 is thenprovided to second circuit subassembly 312. In this manner, the presentinvention can be implemented with legacy devices not equipped with theremote wakeup function.

In summary, in the present embodiment of the present invention, firstcircuit subassembly 310 gives precedence to +5V auxiliary power 302 whenthat source of power is available, and otherwise uses power from +5Vprimary power 330 when that source of power is available. It isappreciated that in other embodiments a different order may be used toassign precedence of one power source over another. In the mannerdescribed above, +5V is provided by first circuit subassembly 310 tosecond circuit subassembly 312.

FIG. 5 is a schematic diagram illustrating second circuit subassembly312 in accordance with one embodiment of the present invention. In thepresent embodiment of the present invention, the +5V received by secondcircuit subassembly 312 from first circuit subassembly 310 can be fromeither +5V primary power 330 or +5V auxiliary power 302 (see discussionpertaining to FIG. 4). Second circuit subassembly 312 also receives+3.3V auxiliary power 332 from another power source (for example, from aPCI bus substantially compliant with revision 2.2 of the PCIspecification).

In accordance with the present invention, second circuit subassembly 312selects either +5V power 540 (from first circuit subassembly 310) or+3.3V auxiliary power 332 to power ASIC 320, thereby addressing thepotential power contention issue that would otherwise occur. In thepresent embodiment, second circuit subassembly 312 selects +3.3Vauxiliary power 332 when that source of power is available. In thiscase, +3.3V auxiliary power can be used to power ASIC 320 and othercomponents such as EEPROM 322 and boot ROM 324. If that source of poweris not available, second circuit subassembly 312 selects +5V power 540from first circuit subassembly 310. In this case, ASIC 320 regulates the+5V to +3.3V, which can then be used to power ASIC 320 and othercomponents such as EEPROM 322 and boot ROM 324. Because ASIC 320 willonly receive either +5V to the input of its voltage regulator, or +3.3Vto the output of its voltage regulator, there will not be any powercontention between the +5V and +3.3V power sources.

Thus, in accordance with the present embodiment of the presentinvention, second circuit subassembly 312 gives precedence to +3.3Vauxiliary power 332 when that source of power is available. It isappreciated that in other embodiments, a different order of precedencemay be used.

With reference still to FIG. 5, in the present embodiment, secondcircuit subassembly 312 includes a plurality of components (510, 511,512, 513, 514 and 515) that operate in combination to arbitrate between+5V power 540 from first circuit subassembly 310 and +3.3V auxiliarypower 332. In the present embodiment, these components are transistors,specifically field effect transistors (FETs). In the present embodiment,transistors 510, 512, 513 and 515 are p-channel FETs, and transistors511 and 514 are n-channel FETs. It is appreciated that in otherembodiments a different number of FETs or different types of FETs may beused in accordance with the present invention.

It is well known in the art how p-channel FETs and n-channel FETsfunction. In general, when V_(SG) is greater than or equal to aspecified voltage, then a p-channel FET is on and will conduct current.Similarly, when V_(GS) is greater than or equal to a specified voltage,then a n-channel FET is on and will conduct current.

In accordance with the present embodiment of the present invention,second circuit subassembly 312 works as follows. For the case in whichboth +5V power 540 from first circuit subassembly 310 and +3.3Vauxiliary power 332 are available, transistor 510 will receive voltagefrom both of these power sources (at source S and gate G, respectively).However, V_(SG) is not large enough to turn on transistor 510.Transistor 511 is on because gate G receives +3.3V from +3.3V auxiliarypower 332 and zero voltage via transistor 510 (also, as will be seen, novoltage from transistor 514). Accordingly, V_(GS) is large enough toturn on transistor 511. Transistor 512 receives +3.3V from +3.3Vauxiliary power 332, and zero voltage from transistors 510 and 511.Accordingly, transistor 512 is on, and therefore +3.3V power 560 isprovided to ASIC 320 (FIG. 3).

Continuing with the case in which both +5V power 540 and +3.3V auxiliarypower 332 are available, transistor 513 receives +5V at source S andzero voltage at gate G. Consequently, V_(SG) is large enough to turn ontransistor 513. Transistor 514 receives approximately +5V fromtransistor 513 (there may be a slight voltage drop across transistor513), and zero voltage from transistors 510 and 511. Thus, transistor514 is off. Transistor 515 receives +5V 540 and approximately +5V fromtransistor 513; however, V_(GS) is not large enough to turn ontransistor 515. Consequently, +5V power 540 is not provided to ASIC 320.

Continuing with reference to FIG. 5, for the case in which +5V power 540is available and +3.3V auxiliary power 332 is not available, thentransistor 510 receives zero voltage from +3.3V auxiliary power 332 atgate G and +5V from +5V power 540 at source S. Consequently, transistor510 is on. Transistor 511 receives approximately +5V from transistor 510and zero voltage from +3.3V auxiliary power 332, and consequentlytransistor 511 is off. Transistor 512 receives zero voltage from +3.3Vauxiliary power 332 and approximately +5V from transistor 510, andconsequently transistor 512 is also off. Transistor 513 receives +5Vfrom +5V power 540 and approximately +5V from transistor 510.Consequently, transistor 513 is off. Transistor 514 receivesapproximately +5V from transistor 510 and zero voltage from transistor513, and so transistor 514 is on. Transistor 515 receives zero voltagefrom transistor 513 and +5V from +5V power 540. Transistor 515 is on andtherefore +5V power 550 is provided to ASIC 320.

Thus, in the present embodiment of the present invention, second circuitsubassembly 312 provides +3.3V auxiliary power 332 to ASIC 320 when+3.3V auxiliary power 332 is available. If +5V power 540 is alsoavailable, then +3.3V auxiliary power 332 takes precedence in accordancewith the present embodiment. If +3.3V auxiliary power 332 is notavailable, then +5V power 540 is used. In this case, +5V power 540 feedsdirectly to the input of the voltage regulator internal to ASIC 320. The+3.3V output of this internal voltage regulator can then be used topower other components such as EEPROM 322 and boot ROM 324.

FIG. 6 is a flowchart of process 600 used to arbitrate between aplurality of power sources connected to NIC 118 (FIG. 3) in accordancewith one embodiment of the present invention. Process 600 can beimplemented for devices (e.g., NIC 118) with or without remote wakeupcapability and for devices that are or are not compliant with PCIspecification revision 2.2. Thus, process 600 can be utilized withlegacy devices.

Starting with step 605 of FIG. 6, in accordance with the presentembodiment, power will be selectively conducted from either +5V primarypower 330 (FIG. 4) or +5V auxiliary power 302 (FIG. 4) using firstcircuit subassembly 310 (FIG. 4).

In step 610 of FIG. 6, only +5V primary power 330 is available. In hiscase, NIC 118 does not have the remote wakeup function through cable 205(FIG. 3) or, alternatively, cable 205 is not connected to connector 300of FIG. 3.

In step 615 of FIG. 6, only +5V auxiliary power 302 is available. Inthis case, computer system 100 of FIG. 3 can be powered down and placedin sleep mode.

In step 620 of FIG. 6, both +5V primary power 330 and +5V auxiliarypower 302 are available.

In step 625, from step 610, first circuit subassembly 310 selects +5Vprimary power 330 to power ASIC 320 (FIG. 3) as described above inconjunction with FIG. 4.

In step 630, from step 615 or step 620, first circuit subassembly 310selects +5V auxiliary power 330 to power ASIC 320 as described above inconjunction with FIG. 4.

Starting with step 635 of FIG. 6, in accordance with the presentinvention, power will be selectively conducted from either +5V power 540(FIG. 5) or +3.3V auxiliary power 332 (FIG. 5) using second circuitsubassembly 312 (FIG. 5).

In step 640 of FIG. 6, only +5V power 540 is available. In this case,for example, NIC 118 is not compliant with revision 2.2 of the PCIspecification.

In step 645, both +5V power 540 and +3.3V auxiliary power 332 areavailable.

In step 650, only +3.3V auxiliary power 332 is available.

In step 655, from step 640, second circuit subassembly 312 selects +5Vpower 540 to power ASIC 320 as described above in conjunction with FIG.5.

In step 660, from step 645 or step 650, second circuit subassembly 312selects +3.3V auxiliary power 332 to power ASIC 320 as described abovein conjunction with FIG. 5.

In step 665, from step 635, if there is no +5V power source (either +5Vprimary or +5V auxiliary) or no +3.3V power source, then there is nopower to the system.

In summary, the present invention provides a device and method thereofwhich address the power contention problem so that components do notinadvertently receive power from more than one source when multiplepower sources are present in a peripheral device (such as a networkinterface card). The present invention also provides a device and methodthereof which allow the peripheral device to select one power sourceversus another depending on the mode in which the computer andperipheral device are currently operating (e.g., sleep mode versusawake). The present invention can be used with devices that have theremote wakeup function and also with devices that are substantiallycompliant with revision 2.2 of the PCI specification. However, thepresent invention can also be used with legacy devices that do not havethe remote wakeup function or are not compliant with revision 2.2 of thePCI specification.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order best toexplain the principles of the invention and its practical application,to thereby enable others skilled in the art best to utilize theinvention and various embodiments with various modifications suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the Claims appended hereto and theirequivalents.

What is claimed is:
 1. A circuit for arbitrating between a plurality ofpower sources connected to a computer system peripheral device, saidcircuit comprising: a first circuit subassembly coupled to a first powersource and a second power source, said first circuit subassembly adaptedto conduct current from said first power source when power is notavailable from said second power source and otherwise conduct currentfrom said second power source; and a second circuit subassembly coupledbetween said first circuit subassembly and a third power source, saidsecond circuit subassembly adapted to conduct current from said thirdpower source when said third power source is available and otherwiseconduct current from said first circuit subassembly, said second circuitsubassembly comprising: a first component coupled to said third powersource and said first circuit subassembly, said first component adaptedto conduct current from said first circuit subassembly when power is notavailable from said third power source and otherwise substantially notconduct current; a second component coupled to said third power sourceand said first component, said second component adapted to conductcurrent from said first component when power is available from saidthird power source and otherwise substantially not conduct current; anda third component coupled to said first component, said second componentand said third power source, said third component adapted to conductcurrent from said third power source when power is available from saidthird power source.
 2. The circuit of claim 1 wherein said firstcomponent, said second component and said third component aretransistors.
 3. The circuit of claim 2 wherein said first component andsaid third component are p-channel field effect transistors (FETs) andsaid second component is a n-channel FET.
 4. The circuit of claim 1wherein said second circuit subassembly further comprises: a fourthcomponent coupled to said first component, said second component andsaid first circuit subassembly, said fourth component adapted to conductcurrent from said first circuit subassembly when power is available fromsaid third power source and otherwise substantially not conduct current;a fifth component coupled to said second component and said fourthcomponent, said fifth component adapted to conduct current from saidfourth component when power is not available from said third powersource and otherwise substantially not conduct current; and a sixthcomponent coupled to said fourth component and said first circuitsubassembly, said sixth component adapted to conduct current from saidfirst circuit subassembly when power is not available from said thirdpower source and otherwise substantially not conduct current.
 5. Thecircuit of claim 4 wherein said fourth component, said fifth componentand said sixth component are transistors.
 6. The circuit of claim 5wherein said fourth component and said sixth component are p-channelFETs and said fifth component is a n-channel FET.
 7. The circuit ofclaim 1 wherein said first circuit subassembly comprises: a seventhcomponent coupled between said first power source and said second powersource, said seventh component adapted to conduct current from saidfirst power source when said second power source is not available and tootherwise conduct power from said second power source; and an eighthcomponent integral with said seventh component, wherein said eighthcomponent is adapted to conduct current from said first power source incombination with said seventh component and to substantially preventcurrent from flowing from said second power source to said first powersource.
 8. The circuit of claim 7 wherein said seventh component is atransistor and said eighth component is a diode.
 9. The circuit of claim1 wherein said first power source is connected to said peripheral devicevia a PCI (peripheral component interconnect) bus and said second powersource is connected to said peripheral device via a cable that providesa remote wakeup function.
 10. The circuit of claim 1 wherein said thirdpower source is connected to said peripheral device via a PCI bussubstantially in accordance with PCI standard 2.2.
 11. The circuit ofclaim 1 wherein said peripheral device is a network adapter.
 12. Amethod for arbitrating between a plurality of power sources connected toa computer system peripheral device, said method comprising the stepsof: a) selectively conducting current from a first power source whenpower is not available from a second power source and otherwiseconducting current from said second power source using a circuitsubassembly coupled to said first power source and said second powersource; b) using a first component to conduct current from said circuitsubassembly when power is not available from a third power source, saidfirst component otherwise not substantially conducting current; c) usinga second component to conduct current from said first component whenpower is available from said third power source, said second componentotherwise not substantially conducting current; and d) using a thirdcomponent to conduct current from said third power source when power isavailable from said third power source; wherein power is conducted fromsaid third power source when power is available from said third powersource and otherwise power is conducted from said circuit subassembly.13. The method for arbitrating between a plurality of power sources asrecited in claim 12 wherein said first component, said second componentand said third component are transistors.
 14. The method for arbitratingbetween a plurality of power sources as recited in claim 13 wherein saidfirst component and said third component are p-channel field effecttransistors (FETs) and said second component is a n-channel FET.
 15. Themethod for arbitrating between a plurality of power sources as recitedin claim 12 further comprising the steps of: e) using a fourth componentto conduct current from said circuit subassembly when power is availablefrom said third power source, said fourth component not otherwisesubstantially conducting current; f) using a fifth component to conductcurrent from said fourth component when power is not available from saidthird power source, said fifth component not otherwise substantiallyconducting current; and g) using a sixth component to conduct currentfrom said circuit subassembly when power is not available from saidthird power source, said sixth component not otherwise substantiallyconducting current.
 16. The method for arbitrating between a pluralityof power sources as recited in claim 15 wherein said fourth component,said fifth component and said sixth component are transistors.
 17. Themethod for arbitrating between a plurality of power sources as recitedin claim 16 wherein said fourth component and said sixth component arep-channel FETs and said fifth component is a n-channel FET.
 18. Themethod for arbitrating between a plurality of power sources as recitedin claim 12 wherein step a) further comprises the steps of: a1)selectively conducting current from said first power source using aseventh component coupled between said first power source and saidsecond power source; and a2) conducting current from said first powersource and substantially preventing current from flowing from saidsecond power source to said first power source using an eighth componentintegral with said seventh component; wherein power from said secondpower source is conducted when power is available from said second powersource, and otherwise power from said first power source is conducted.19. The method for arbitrating between a plurality of power sources asrecited in claim 18 wherein said seventh component is a transistor andsaid eighth component is a diode.
 20. The method for arbitrating betweena plurality of power sources as recited in claim 12 wherein said firstpower source is connected to said peripheral device via a PCI(peripheral component interconnect) bus and said second power source isconnected to said peripheral device via a cable that provides a remotewakeup function.
 21. The method for arbitrating between a plurality ofpower sources as recited in claim 20 wherein said third power source isconnected to said peripheral device via a PCI bus substantially inaccordance with PCI standard 2.2.
 22. The method for arbitrating betweena plurality of power sources as recited in claim 12 wherein saidperipheral device is a network adapter.
 23. A circuit for arbitratingbetween a plurality of power sources connected to a computer systemperipheral device, said circuit comprising: a first circuit subassemblycoupled to a first power source and a second power source, said firstcircuit subassembly adapted to conduct current from said first powersource when power is not available from said second power source andotherwise conduct current from said second power source; and a secondcircuit subassembly coupled between said first circuit subassembly and athird power source, said second circuit subassembly adapted to conductcurrent from said third power source when said third power source isavailable and otherwise conduct current from said first circuitsubassembly, said second circuit subassembly comprising: a firsttransistor coupled to said third power source and said first circuitsubassembly, said first transistor adapted to conduct current from saidfirst circuit subassembly when power is not available from said thirdpower source and otherwise substantially not conduct current; a secondtransistor coupled to said third power source and first transistor, saidsecond transistor adapted to conduct current from said first transistorwhen power is available from said third power source and otherwisesubstantially not conduct current; a third transistor coupled to saidfirst transistor, said second transistor and said third power source,said third transistor adapted to conduct current from said third powersource when power is available from said third power source; a fourthtransistor coupled to said first transistor; said second transistor andsaid first circuit subassembly, said fourth transistor adapted toconduct current from said first circuit subassembly when power isavailable from said third power source and otherwise substantially notconduct current; a fifth transistor coupled to said second transistorand said fourth transistor, said fifth transistor adapted to conductcurrent from said fourth transistor when power is not available fromsaid third power source and otherwise substantially not conduct current;and a sixth transistor coupled to said fourth transistor and said firstcircuit subassembly, said sixth transistor adapted to conduct currentfrom said first circuit subassembly when power is not available fromsaid third power source and otherwise substantially not conduct current.24. The circuit of claim 23 wherein said first power source is connectedto said peripheral device via a PCI (peripheral component interconnect)bus, said second power source is connected to said peripheral device viaa cable that provides a remote wakeup function, and said third powersource is connected to said peripheral device via a PCI bussubstantially in accordance with PCI standard 2.2.
 25. The circuit ofclaim 23 wherein said peripheral device is a network adapter.
 26. Thecircuit of claim 23 wherein said first circuit subassembly comprises: aseventh transistor coupled between said first power source and saidsecond power source, said seventh transistor adapted to conduct currentfrom said first power source when said second power source is notavailable and to otherwise conduct power from said second power source;and a diode integral with said seventh transistor, wherein said diode isadapted to conduct current from said first power source in combinationwith said seventh transistor and to substantially prevent current fromflowing from said second power source to said first power source.